Job Description
On-site in Austin, TX, & five days a week.
Masters in Electrical Engineering, Computer Engineering, or related field.&
Experience with MATLAB DSP prototyping and translation to System C.&
10+ years of experience in DSP design and modelling, preferably for communications or optical systems.&
Strong proficiency in System C / C++, with hands-on experience building modular simulation frameworks.&
Solid understanding of digital communication systems (modulation, coding, equalization, carrier and timing recovery).&
Knowledge of coherent optical communications.&
Familiarity with fixed-point modelling and ASIC/DSP design flow.&
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Key Responsibilities &Develop a comprehensive System C simulation platform that models the entire optical DSP system, including TX/RX data-paths in fixed-point, Analog front-end models, transmit/receive optical subassembly models and FW.&
Collaborate with DSP algorithm engineers to translate MATLAB models into efficient System C modules.&
Define simulation frameworks that integrate timing recovery loop, equalization, carrier recovery loop, FEC, DAC/ADC models and optical models (both components and fibre channels).&
Support system-level performance analysis (BER, EVM, OSNR sensitivity) under realistic channel and noise models.&
Develop regression and verification environments to ensure functional correctness and robustness of the DSP chain.&
Document architecture, APIs, and simulation methodologies for cross-team use.&
MSc in Electrical Engineering, Computer Engineering, or related field.&
Experience with MATLAB DSP prototyping and translation to System C.&
10+ years of experience in DSP design and modelling, preferably for communications or optical systems.&
Strong proficiency in System C / C++, with hands-on experience building modular simulation frameworks.&
Solid understanding of digital communication systems (modulation, coding, equalization, carrier and timing recovery).&
Knowledge of coherent optical communications.&
Familiarity with fixed-point modelling and ASIC/DSP design flow.&
Excellent problem-solving and teamwork skills.&
Familiarity with verification methodologies (UVM/SystemVerilog) and HW/SW co-simulation.&
Knowledge of hardware description languages (VHDL/Verilog) or HLS flows.&
Exposure to FEC codes (LDPC, RS, OFEC) and their integration into DSP systems.&
Understanding of jitter, PLL/CDR modelling, and mixed-signal impairments in simulations.&
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